How a single AI accelerator is conjured from quartz, and why the chain that builds it is the most geographically concentrated industrial system humanity has ever depended on — engineered, layer by layer, into a structure that is robust by inventory, not by design.
The AI compute supply chain works every day. That is precisely what makes it dangerous: its reliability is the product of vast accumulated inventory, decades of tacit process knowledge, and a handful of firms operating without redundancy — not the product of structural resilience. It has no second source for its most critical inputs. It cannot be redesigned on any timescale shorter than a decade, and it cannot be skipped.
TSMC fabricates ~92% of all sub-7nm AI logic. Every Blackwell GPU, every Google TPU, every AWS Trainium, every Microsoft Maia passes through fabs clustered on the western edge of Taiwan. A halt is estimated at a ~$2.5 trillion global shock — roughly 11% of US GDP — in year one.
The binding constraint is no longer the transistor — it is advanced packaging (CoWoS) and HBM. Both are sold out for 2026. NVIDIA alone books an estimated ~60% of 2025 CoWoS capacity and >70% of the CoWoS-L variant. SK Hynix has sold its entire 2026 HBM output.
US AI data-center load rises from ~80 GW (2025) toward ~150 GW (2028). The PJM interconnect queue alone exceeds 2,600 GW; large transformers run 3–7 year lead times. ~30% of new 2026 capacity is being designed to bypass the grid entirely.
Before the supply chain makes sense, the object has to. A modern AI accelerator is a slab of near-perfect crystalline silicon into which tens of billions of switches have been printed at a scale smaller than visible light. Everything downstream — the monopolies, the chokepoints, the $380M machines — exists to solve one problem: drawing reliably at that scale.
Silicon is a semiconductor — it conducts only when you tell it to. By doping it with trace impurities (boron, phosphorus) you create regions of excess positive or negative charge. Join them and you get a p–n junction: a one-way gate for electrons. Pack billions of these gates as transistors and you have a device that computes by switching. The art is making each switch smaller, faster, and less leaky than the last.
Transistors are printed onto a polished disc of monocrystalline silicon — the wafer (today 300mm across). Hundreds of identical rectangles are patterned across it; each is a die. The wafer is sliced into individual dies, the good ones packaged into the black rectangle you call a chip. Modern transistors are 3-D: FinFET gave way to gate-all-around (GAA / nanosheet) at the 3nm/2nm nodes, wrapping the gate on all four sides to stop current leaking.
Six terms account for most of the confusion in any supply-chain discussion. Learn these and the rest of this report reads cleanly.
The journey starts not with "sand" in any beach sense but with unusually pure quartz, most of it from one valley in North Carolina. Five transformations stand between that rock and a wafer flat enough to print on.
It begins at Spruce Pine, North Carolina, source of an estimated 70–90% of the world's high-purity quartz — the feedstock for the crucibles and, indirectly, the silicon itself. Two operators (Sibelco/IOTA and The Quartz Corp) work the deposit. When Hurricane Helene hit in September 2024, buffers held — but the concentration is total.
Quartz (SiO₂) is smelted with carbon in an arc furnace: SiO₂ + 2C → Si + 2CO. The output is ~98–99% "metallurgical-grade" silicon — nowhere near pure enough for electronics, but the necessary first step.
Metallurgical silicon is converted to trichlorosilane gas, then deposited back as hyper-pure polysilicon — "eleven nines" (99.999999999%) purity. Wacker (Germany) and Hemlock (US) dominate semiconductor-grade supply, together roughly ~75%. This is where most of the world's polysilicon value sits.
Polysilicon is melted in a quartz crucible and a seed crystal slowly pulled and rotated to grow a single cylindrical ingot (boule) up to 300mm in diameter. The deep irony: the crucible is the chokepoint, not the feedstock — those crucibles are themselves made from Spruce Pine quartz.
The ingot is sawn into wafers, then lapped, chemically-mechanically polished (CMP) to near-atomic flatness, and finished with an epitaxial layer. The result is flat to within a few atoms across 300mm — the canvas everything else is printed on.
Polished wafers are a near-duopoly hiding inside a quasi-monopoly. Shin-Etsu and SUMCO (both Japan) hold ~50–54% combined; the top five makers ~82–85%. The industry collectively abandoned the move to 450mm wafers in 2017 — meaning every fab on Earth is locked to 300mm for the foreseeable future, and the people who make those discs can be counted on one hand.
A chip is not printed once. An advanced logic process stacks 50–100+ patterned layers, each built by running the same cycle — clean, coat, expose, develop, etch, deposit, planarize — over and over, with nanometre alignment between passes. This loop is the beating heart of the fab, and the exposure step inside it is the single thing that decides how small you can go.
For decades, deep-ultraviolet (DUV, 193nm) light did the printing. Below ~7nm, the wavelength is simply too coarse: chipmakers resorted to multipatterning — exposing the same layer 3–4 times with offset masks — which is slow, costly, and yield-killing. Extreme-ultraviolet (EUV, 13.5nm) light prints those features in a single pass. This is the dividing line between SMIC's captive 7nm-on-DUV and TSMC's clean 3nm/2nm.
Everything above the 7nm line — i.e. every competitive AI accelerator made today — requires EUV. There is exactly one company on Earth that makes an EUV machine. Multipatterning lets a sanctioned fab limp to 7nm without it, but not to 3nm at economic yield. The wavelength, not the willpower, is the wall.
An EUV scanner is arguably the most sophisticated device humans manufacture for commercial sale — and ASML in Veldhoven, the Netherlands, is the only place on the planet that builds one. The machine is itself a supply chain: ASML integrates components that are each single-sourced from one other firm.
“If you were to enlarge such an EUV mirror to the size of Germany, the largest unevenness — the Zugspitze, so to speak — would be a whole 0.1 millimetre.” — Carl Zeiss SMT, on the Mo/Si multilayer mirrors at the heart of every EUV scanner. The sensors and actuators that hold them still are precise enough, Zeiss claims, to “hit a golf ball on the surface of the moon with the deflected laser beam.”
ASML does not really build the scanner alone. Three single points of failure sit upstream of it — and ASML either acquired them outright or took an equity stake to keep them solvent and aligned.
Oberkochen, Germany. Exclusive supplier of projection/illumination optics and the Mo/Si multilayer mirrors. ASML took a 24.9% stake for ~€1B in 2016 to fund High-NA optics.
Ditzingen, Germany. Sole supplier of the CO₂ drive laser — 20 mJ pulses at 50 kHz, the most powerful pulsed industrial laser in the world.
San Diego. Designer of the EUV source module — droplet generator, vessel, collector. ASML acquired it in 2013 for €1.95B because its source progress was the gating item.
EUV grew out of the 1997 EUV LLC consortium — Intel, Motorola, AMD and the US DOE labs. Nikon and Canon were excluded from the IP and have no EUV product today. In 2012 Intel committed ~$4.1B for 15% of ASML; TSMC and Samsung added ~$1B each. Total EUV-ecosystem R&D over three decades: $14–21B. EUV scanners have never been sold to China — and even if one were, the ~5,000-supplier web, the installation teams, and the tacit knowledge do not transfer. China's SMEE reached 90nm ArF in 2025; domestic sub-10nm lithography is judged unlikely before 2030. This is why SMIC tops out at 7nm via multipatterning.
EUV gets the headlines, but a fab is a parade of equipment monopolies. Five firms — ~89% of all wafer-fab equipment by revenue — supply the deposition, etch, and metrology tools without which no chip is made.
| Firm | Country | FY24 revenue | Franchise |
|---|---|---|---|
| Applied Materials | USA | $27.18B | Deposition, ion implant, CMP — the broadest tool line |
| ASML | Netherlands | ~$30B | Lithography — EUV monopoly + DUV |
| Lam Research | USA | $16.2B | Etch & deposition; the new Vantex cryo-etcher |
| Tokyo Electron | Japan | $16.0B | Coat/develop track (~89% share), etch, clean |
| KLA | USA | $10.85B | Process control & inspection — near-monopoly in metrology |
The moat is not static — ASML is already one generation ahead of what is in volume production, and the transistor itself is being rebuilt around a second new idea. Both deepen the same dependency.
Today's volume EUV runs at 0.33 numerical aperture. The successor, High-NA (0.55 NA, the EXE:5000/5200 series), resolves finer features in a single exposure — buying a node or two without a return to multipatterning. The cost: anamorphic optics that magnify 8× in one axis and 4× in the other, which halves the printable field. Big dies must be stitched from two half-fields, a fresh yield tax. At ~$380M a unit and ~150-tonne install, the first systems went to Intel and the usual three; it does nothing to widen the supplier base — it narrows it.
As wires shrink, power and signal lines fight for the same crowded top of the chip. Backside power delivery (BSPDN) — Intel's PowerVia, TSMC's Super Power Rail at the ~2nm/A16 generation — moves the power network to the underside of the wafer, freeing the front for signal routing and cutting voltage droop. It pairs with gate-all-around (GAA / nanosheet) transistors already noted above. The catch: it demands extreme wafer thinning, through-silicon nano-TSVs, and double-side processing — more steps, more tools, and yield learning that, again, lives almost entirely inside TSMC, Intel and Samsung.
Between the silicon die and the circuit board sits the package substrate — a dense, multilayer interposer that fans the chip's thousands of connections out to the world. The insulating material that makes it possible is Ajinomoto Build-up Film (ABF), created by the Japanese maker of MSG seasoning, and it holds an estimated 95–99% of the market.
A high-end FC-BGA substrate for an AI accelerator stacks 20+ build-up layers of ABF, each carved with fine wiring. An NVIDIA B200 mounts two ~800mm² dies on a CoWoS-L package — and that whole assembly rides on an ABF-based substrate. The film market itself is tiny — only ~$0.5–0.6B in annual sales — yet without it there is no advanced package, anywhere.
Top five ≈ 74% of FC-BGA substrate. Ibiden was historically NVIDIA's exclusive substrate partner; Unimicron was added as a second source in 2025.
With Ajinomoto at 95–99% of ABF, a single plant fire or disruption translates to an estimated 4–8 week depletion of downstream substrate inventory. The structural fix — glass-core substrates, which Intel and others are pursuing — is real but 5–10 years from displacing ABF at volume. Until then, a condiment company is load-bearing for the global AI build-out.
For the AI build-out, the binding constraint is no longer the transistor — it is advanced packaging. TSMC's CoWoS (Chip-on-Wafer-on-Substrate) places the GPU die and its stacks of HBM side-by-side on a silicon interposer, wiring them together with bandwidth a circuit board could never deliver. Demand has outrun capacity for two straight years.
Beyond placing dies side-by-side, SoIC (System-on-Integrated-Chips) bonds them face-to-face with hybrid copper-to-copper bonding at sub-10µm pitch — direct Cu–Cu contact at roughly 0.05 pJ/bit, the technique behind AMD's 3D V-Cache. The bonders themselves are another oligopoly: BESI, Applied Materials, EVG, TEL, ASMPT.
NVIDIA books an estimated ~60% of 2025 CoWoS and >70% of CoWoS-L. The top four accelerator designers together consume an estimated ~90% of all CoWoS + HBM in 2025. A disruption here has an estimated 2–3 year recovery — you cannot build a packaging line, or train its staff, on demand.
Outside TSMC's in-house CoWoS, the broader assembly/test industry (OSAT) is led by a Taiwan + China cluster. Top-10 OSAT revenue ~$41.56B; Taiwan + China hold >65%; APAC overall ~72.9%.
| OSAT | Country | Revenue | Share | Note |
|---|---|---|---|---|
| ASE Technology | Taiwan | $18.54B | ~45% | Incl. SPIL; the clear leader |
| Amkor | USA/Korea | $6.32B | ~15% | CoWoS overflow partner; Arizona buildout |
| JCET | China | $5.00B | ~12% | +19.3% YoY — fastest grower |
| Tongfu | China | $3.32B | ~8% | Close AMD packaging ties |
| Powertech (PTI) | Taiwan | $2.28B | ~5.5% | Memory packaging specialist |
An AI accelerator is useless without memory fast enough to feed it. High-Bandwidth Memory (HBM) solves this by stacking DRAM dies vertically and wiring them through the silicon with through-silicon vias (TSVs), then mounting the stack micrometres from the GPU on the CoWoS interposer. It is the single tightest input in the entire chain.
The two leaders bond their stacks differently. SK Hynix uses MR-MUF (mass-reflow molded underfill), injecting protective compound under the whole stack at once. Samsung uses TC-NCF (thermal-compression non-conductive film). With HBM4 the base die moves to a TSMC 12nm logic process — a structural shift that makes even memory dependent on Taiwan.
SK Hynix has stated its entire 2026 HBM output is sold out. There is ~0% HBM fabricated in the US before 2028. HBM TAM is projected to leap from ~$38B → ~$58B (2025→2026). Early HBM4 yields run an estimated 50–60%.
An HBM bit consumes roughly 3× the wafer area of a standard DRAM bit. As the big three convert capacity to HBM to chase AI margins, commodity DRAM supply tightens — feeding an estimated ~20% rise in DRAM prices into 2026. The AI build-out is now visibly raising the cost of memory in every laptop and phone on Earth.
The whole stack on one page. Material flows upward — from raw ore at the base to deployed clusters at the top — and every layer is gated by a handful of firms, color-coded here by function. The right rail flags where the supply chain is most likely to snap. Where one layer feeds the next, it cannot be skipped.
The chain is not just concentrated by firm — it is concentrated by place. East Asia holds logic, memory, packaging, and assembly within a few hundred kilometres of the Taiwan Strait. The Netherlands holds lithography. A single North Carolina county holds the quartz. China holds the minerals. Pins are numbered; the key below maps each to its function.
One layer up from the foundry sits the part everyone names — the accelerator itself, and the company that owns ~9 of every 10 sold. But the more interesting story of 2025 is the hyperscaler revolt: Google, Amazon, Microsoft, Meta and OpenAI all designing their own chips to escape NVIDIA's pricing. The escape works — right up until it hits the same two chokepoints everyone else hits.
In data-center GPUs, NVIDIA holds ~94% unit share, with AMD ~5% and Intel ~1% (Jon Peddie Research, 2024). But the deeper lock-in is software: CUDA, NVIDIA's 18-year-old programming ecosystem, is the switching cost that keeps buyers captive even when competing silicon is cheaper per FLOP. It is, on any honest accounting, the second-largest single point of failure in the entire chain after Taiwan itself — and the only one that is purely artificial.
No chip — NVIDIA's or anyone's — is designed without electronic design automation software. Three firms own it: Synopsys (~31%), Cadence (~30%) and Siemens EDA (~13%) — together >74%. Add Arm instruction-set IP underneath, and the design layer has its own quiet triopoly that even the hyperscalers cannot route around. In September 2025 NVIDIA took a $5B equity stake in Intel at $23.28/share — a competitor becoming a stakeholder, a sign of how few independent nodes remain.
Custom silicon is real and growing: Broadcom alone reported an AI revenue backlog above $73B exiting 2025, almost all of it hyperscaler ASIC and networking work. But read the diagram literally — the in-house chips escape NVIDIA's margin, not the industry's geography. Google's TPU, AWS's Trainium, Microsoft's Maia and Meta's MTIA are all fabricated by TSMC and all fed by Korean HBM. The revolt redistributes profit among American firms; it does not move a single wafer off Taiwan.
The same dependency graph from section 09, re-told as a reference index. Each layer is a tier of value-add; the apex (Layer 5) is where the whole pyramid balances on one company on one island. Expand any layer.
The West controls the tools, the foundry, and the designs. China controls the dirt. When the US tightened equipment and chip export controls, Beijing reached for the one layer it dominates — the bottom one — and demonstrated it could squeeze upward.
These are not designed monopolies — they are the product of two decades of accepting the dirty, low-margin refining the rest of the world offshored. The leverage is real precisely because nobody else wanted this layer.
The US Geological Survey modeled a total Chinese gallium-and-germanium ban: it estimated a ~$3.4B hit to US GDP, with gallium prices potentially rising ~150% and germanium ~26%. This is the structural answer to why export-control hawks cannot simply tighten indefinitely — the bottom of the stack can push back on the top.
One widely-repeated mineral chokepoint is now mostly historical. Neon — critical for older DUV lasers — was ~50% sourced from two Ukrainian firms (Ingas, Cryoin) before 2022. The war spiked prices, but the industry adapted: in-tool neon recycling now reclaims the bulk of it, fresh capacity came online (including Linde in Texas), and crucially EUV lithography uses no neon at all. The lesson cuts both ways — concentrated inputs are dangerous, but a determined industry can engineer around a gas in a few years. It cannot engineer around TSMC in the same window.
Concentration is easier to see in dollars than in diagrams. Below is calendar-year 2024 revenue for the dominant firm at each tier — reconciled to a single epoch so the figures are actually comparable. They are not.
| Layer | Dominant firm | CY2024 revenue | Position |
|---|---|---|---|
| Design (GPU) | NVIDIA | $130.5B ($115.2B DC) | ~94% data-center GPU |
| Foundry | TSMC | ~$90B | ~92% sub-7nm; 69.9% foundry rev |
| Memory (total) | Samsung | ~$63B memory | #2 HBM, #1 overall DRAM |
| HBM leader | SK Hynix | $48.6B | ~57–62% HBM |
| Equipment | ASML | ~$30B | 100% EUV monopoly |
| Equipment | Applied Materials | $27.2B | #1 deposition/etch |
| IDM | Intel | $43.1B | ~1% AI GPU; foundry pivot |
| Memory #3 | Micron | $25.1B | ~21% HBM |
| Packaging / OSAT | ASE Technology | $18.5B | ~45% OSAT |
Most "supply chain" comparisons are quietly broken because they mix epochs and segments. NVIDIA's $130.5B is total fiscal-year revenue; its data-center segment alone is $115.2B; comparing either to TSMC's ~$90B foundry revenue is apples-to-oranges (NVIDIA is fabless — TSMC's revenue is partly inside NVIDIA's cost line). Samsung's "memory" number folds DRAM, NAND, and HBM together. Always ask three questions before trusting a market-share figure: which quarter, which segment definition, and which analyst house — Counterpoint, TrendForce and Bloomberg routinely differ 5–10 points on HBM share alone.
Twelve points where the chain is most likely to break, ordered worst-first. The meter shows relative severity; red is catastrophic and effectively irreplaceable on any near-term horizon.
~92% of sub-7nm AI logic on one island. No substitute before 2028. Worst-case disruption: up to $2.5T US losses, ~11% GDP fall (2022 SIA/McKinsey scenario via NYT).
Absolute Dutch monopoly (100%); Zeiss SMT optics and TRUMPF/Cymer sources are themselves single-sourced. Only ~48 EUV systems shipped in FY2025.
95–99% of the insulating build-up film under every high-performance processor — a food-company byproduct with no qualified substitute. The most underrated single-firm dependency in the stack.
TSMC's CoWoS is the active 2025–2026 throttle on accelerator output. Sold out through 2026; NVIDIA absorbs ~60% of capacity and >70% of CoWoS-L.
Sold out through 2026; ~79% Korean (SK Hynix / Samsung / Micron). SK Hynix is NVIDIA's primary supplier; HBM4 base die folds into the TSMC foundry chokepoint.
The fastest-tightening 2026 constraint. ~80→150 GW demand by 2028, 3–7 year transformer lead times, multi-thousand-GW interconnection queues. Megawatts now gate compute.
~99% gallium, ~90% rare-earth refining, ~93% magnets. Wielded through 2023–2025, suspended 12 months post-APEC — but the legal apparatus remains fully intact.
EUV photoresists ~80–90% Japan-controlled (JSR, Tokyo Ohka, Shin-Etsu, Fujifilm). A narrow, high-purity chemistry with no quick second source.
A two-company, single-county vulnerability for crucible-grade quartz (~70–90%). Partly insured by recent investment and Norwegian buffer stocks.
Electrostatic chucks and fine ceramics ~80%+ Japan (TOTO, NGK, Kyocera, Niterra). Invisible until an earthquake or fire takes a single plant offline.
Synopsys + Cadence + Siemens EDA >74% combined — the only viable design toolchain. Used briefly as a US export-control lever in 2025.
Indirect but real exposure for batteries, magnets, and specialty alloys. Less acute for logic, but a structural dependency at the materials layer.
What each actor should actually do, separated by time horizon. The unifying logic: you cannot fix Taiwan in the near term, so near-term moves are about inventory and second-sourcing; structural moves are about geography.
Stockpile what you cannot second-source (HBM, ABF, resist), second-source what you can (packaging, power, EDA-adjacent tooling), and accept that the foundry layer is a geopolitical problem with an engineering price tag measured in years and hundreds of billions — not a procurement problem you can solve with a purchase order.
Where this report is soft, it says so. Read these before quoting any single number as gospel.